Please use this identifier to cite or link to this item:
Title: An internal schematic view and simulation of major diagonal mesh network-on-chip
Authors: Sharma S.K
Jain A
Gupta K
Prasad D
Singh V.
Keywords: MD-Mesh
Network-on-Chip (NoC).
Issue Date: 2019
Publisher: American Scientific Publishers
Abstract: NoC is a competent communication for on chip network architectures. It make more efficient the computational and high congestion communication on a single chip. In this paper, we are proposing a NoC topologies, i.e., Major Diagonal Mesh NoC called MD-Mesh NoC. In MD-Mesh NoC the corner of major diagonal linked with each other so that the efficiency of the communication among the corner can be increase. The internal semantic view and register transfer logic (RTL) View has been shown. As number of connections among the nodes increases and number of hopes decreases, performance of packet traversing will get increases. The synthesis and simulation has been done on Vertex 5 FPGA. The hardware parameters like number of slices and memory usage with respect to increase the number of nodes has been calculated on FPGA Vertex 5.
URI: 10.1166/jctn.2019.8534
Appears in Collections:Journals

Files in This Item:
There are no files associated with this item.

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.