Different configuration of low-power memory design using capacitance scaling on 28-nm field-programmable gate array

Abstract

A real capacitor will have some power dissipation, whereas an ideal capacitor will not dissipate any power. In this paper, we designed a capacitance scaling-based low-power RAM design. Our work aims to analyze how the memory circuit works using capacitance scaling does and varying temperatures. This design is implemented in Verilog. Usually, for the functioning of a device, the junction temperature is below 125 �C. If we scale down frequency from 10 to 4.5 GHz, 2.3 and 1 GHz then there is 42.96, 59.03, and 70.4% reduction, respectively, in total power at 5 pF output load. With the increase in capacitance, there should be the increase in junction temperature. But the novelty of our work is that we can control the effect of capacitance scaling on junction temperature with the help of addition airflow of 500 Linear Feet per Minute (LFM). � 2018, Springer Nature Singapore Pte Ltd.