LVCMOS-based frequency-specific processor design on 40-nm FPGA

Abstract

This paper shows a power efficient processor design using LVCMOS and HSTL I/O standards. We have compared the performance of our processor through different frequencies. To increase the performance, code of the processor has been remodified by using I/O standards. On remodification of code at different operating frequencies, a significant reduction in logic power, clock power, IO power, signal power and thus total power dissipation is observed. By doing power analysis, the best results are obtained by using LVCMOS12. This paper provides a novel FPGA-based design for power efficient processor. � Springer Nature Singapore Pte Ltd. 2018.