Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/2167
Title: Power Efficient Arithmetic and Logical Unit Design on FPGA
Authors: Kaushik B
Anand V
Yasmeen K
Kaur A.
Keywords: FPGA
Frequency Scaling
IO Standard
LVCMOS
Xilinx
Issue Date: 2018
Publisher: Institute of Electrical and Electronics Engineers Inc.
Abstract: Arithmetic Logic Unit (ALU) is one of the most crucial part of all the digital circuits that is used to perform arithmetic and logical operations. An energy and power efficient ALU is designed in this paper by employing different energy and power efficient techniques. ALU is designed on ISE project navigator of Xilinx software and power analysis is done on X Power Analyzer. Two energy efficient techniques named as Frequency scaling and Input/Output (I/O) standard scaling are employed on ALU. In the frequency scaling technique, frequency range of the design is varied from Mega Hertz (MHz) to Tera Hertz (THz) and power analysis is done to figure out the most efficient frequency in terms of power consumption. Power analysis is also done at different I/O standards of Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) logic family to find out the most power efficient IO standard. The device is operated on ARTIX-7 FPGA technology with a channel length of 28 nano meters (nm). It has been concluded from results that maximum power is being saved at LVCMOS 33 I/O standard at a frequency of 1MHz. � 2018 IEEE.
URI: 10.1109/WECON.2018.8782051
http://hdl.handle.net/123456789/2167
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