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|Title:||A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA|
|Keywords:||Field Programmable Gate Arrays (FPGA)|
Advanced Encryption Standard (AES) algorithm
Slice Register (SR)
Look Up Tables (LUTs)
Input/Output (I/O) and Global Buffer (BUFG)
|Publisher:||Institute of Electrical and Electronics Engineers Inc.|
|Abstract:||As the technology is getting advanced continuously the problem for the security of data is also increasing. The hackers are equipped with new advanced tools and techniques to break any security system. Therefore people are getting more concern about data security. The data security is achieved by either software or hardware implementations. In this work Field Programmable Gate Arrays (FPGA) device is used for hardware implementation since these devices are less complex, more flexible and provide more efficiency. This work focuses on the hardware execution of one of the security algorithms that is the Advanced Encryption Standard (AES) algorithm. The AES algorithm is executed on Vivado 2014.2 ISE Design Suite and the results are observed on 28 nanometers (nm) Artix-7 FPGA. This work discusses the design implementation of the AES algorithm and the resources consumed in implementing the AES design on Artix-7 FPGA. The resources which are consumed are as follows-Slice Register (SR), Look-Up Tables (LUTs), Input/Output (I/O) and Global Buffer (BUFG).|
|Appears in Collections:||Conferences|
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