Effective Data Transmission with UART on Kintex-7 FPGA

Abstract

Fast data communication is the need of today's generation. This is because of the advancements and growth of technologies. This research work is about the implementation and analysis of data communication of Universal Asynchronous Receiver Transmitter (UART) on Kintex-7 Field Programmable Gate Array (FPGA) at different clock periods. The implementation is done on the VIVADO tool and analysis of data communication for different clock time is done by timing summary option available on the VIVADO tool. It is observed that data communication takes place in UART when the clock period is 3ns or more than 3ns because for the data transfer Worst Negative Slack (WNS) and Worst Hold Slack (WHS) both must be positive and Total Hold Slack (THS) and Total Negative Slack (TNS) should be 0.000. If the clock period is less than 3ns no data transfer will take place.