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Title: Injecting Power Attacks with Voltage Glitching and Generation of Clock Attacks for Testing Fault Injection Attacks
Authors: Kaur S
Singh B
Kaur H
Gupta L.
Keywords: Fault injection attack
Clock glitch attack
Positive fault attack|\Negative fault attack
Cadence virtuoso
Issue Date: 2021
Publisher: Lecture Notes in Electrical Engineering
Abstract: Fault injection attacks pose serious threat in security of embedded devices since they require less expertise to conduct them. Suitable countermeasures can only be built if there effects are studied and analyzed in detail. This paper presents circuits which produces power fault injection attack (positive, negative, positive/negative) through voltage glitching on cadence 180 nm technology node. Additionally, it presents a VHDL code for generating clock fault (overclocking and underclocking attacks) injection attack. Effect of power and clock fault injection attacks is analyzed on combinational circuits. Techniques presented in this paper can be used as testing platforms for doing analysis of fault injection attacks on different combinational and sequential circuits so that countermeasures can be built in future in order to have attack-resistant devices. The paper emphasizes the perspective from the attacker, rather than the perspective of countermeasure development.
URI: 10.1007/978-981-15-7804-5_3
Appears in Collections:Conferences

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